Write a VHDL program to design a 1:8 Demux using Data flow modeling

Below is a VHDL program for a 1:8 Demux using Data Flow Modeling:

<pre>

“`vhdl
— 1:8 Demux using Data Flow Modeling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Demux1to8 is
Port (
Sel : in STD_LOGIC_VECTOR(2 downto 0); — 3-bit input for select lines
Input : in STD_LOGIC; — Input signal
Y : out STD_LOGIC_VECTOR(7 downto 0) — 8 outputs
);
end entity Demux1to8;

architecture dataflow of Demux1to8 is
begin
process (Sel, Input)
begin
case Sel is
when “000” =>
Y <= (Input, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’);
when “001” =>
Y <= (‘0’, Input, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’);
when “010” =>
Y <= (‘0’, ‘0’, Input, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’);
when “011” =>
Y <= (‘0’, ‘0’, ‘0’, Input, ‘0’, ‘0’, ‘0’, ‘0’);
when “100” =>
Y <= (‘0’, ‘0’, ‘0’, ‘0’, Input, ‘0’, ‘0’, ‘0’);
when “101” =>
Y <= (‘0’, ‘0’, ‘0’, ‘0’, ‘0’, Input, ‘0’, ‘0’);
when “110” =>
Y <= (‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, Input, ‘0’);
when others =>
Y <= (‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, Input);
end case;
end process;
end architecture dataflow;
“`

</pre>

In this code, we define an entity `Demux1to8` with three inputs: `Sel` for the select lines (3 bits), `Input` for the input signal, and eight outputs `Y` representing the demultiplexer outputs. We use the `case` statement to demultiplex the input signal based on the select lines. The selected output is driven high with the input value, while all other outputs are driven low.